By selective area growth (SAG) technique, we selectively grow epitaxial III-V semiconductors on exposed regions of a substrate otherwise covered with a dielectric layer. One application of this technique is to grow in-plane nanowires as scalable platforms for quantum information processing. With subsequent deposition of a superconductor, this material system can induce topological superconducting phases that host Majorana zero modes. Our group develops the SAG nanowire-superconductor systems to scale up nanowire networks essential for building topological quantum bits towards a scalable quantum computer.
Another application of SAG is to laterally grow III-V epitaxial layers for fabricating novel semiconductor devices such as tunnel field-effect-transistors (Tunnel FETs). To laterally grow epitaxial films, pre-fabricated dielectric templates are used to confine the growth and its direction, also known as Confined Epitaxial Lateral Overgrowth (CELO). This allows a complete control of pre-defined fin thicknesses and building lateral in-plane heterojunctions which can pave the way for fabricating low-power high-on-current Tunnel FETs, virtual substrates for photonic devices as well as III-V on Si integration.